There seems to be a good number of people who are blogging on SystemVerilog. And a good percentage of these blogs are powered by wordpress.
When I set off blogging, I kind of missed a good syntaxhighlighter for SystemVerilog. Well there are a number of wordpress plugins that do syntax highlighting job for you, but none supports SystemVerilog.
Fortunately, I found that SyntaxHighlighter Evolved Plugin supports extensions. So I went ahead and created an extension in form of an add-on plugin.
So, if you are a SystemVerilog geek, and want to share your code snippets with others, go ahead and use this small plugin. Note that this plugin depends on an active installation of SyntaxHighlighter Evolved Plugin.
Download
SyntaxHighlighter add-on for SystemVerilog
Install
Install and activate SyntaxHighlighter Evolved first.
Upload the systemverilog-syntax.zip on to the plugin interface of your wordpress installation. Activate the plugin.
Usage
When you have a SV code snippet to share, enclose it within
1
tags. As an example, if you wanted to share a code that looks like ....
`ifndef _FOO_SV_
`define _FOO_SV_
class foo extends bar;
rand int frop;
constraint frop_cst
{
// ....
};
// More code here
endclass: foo
`endif // _FOO_SV_
You need to just enclose it inside sv tags -- just as illustrated below here.
1
This should result in a beutified snippet on your weblog.
`ifndef _FOO_SV_
`define _FOO_SV_
class foo extends bar;
rand int frop;
constraint frop_cst
{
// ....
};
// More code here
endclass: foo
`endif // _FOO_SV_
Facing issues? Just leave out a comment.
