Monthly archives: November 2009

A note on VMM Channel and its Parameterization

27Nov09

I just wrapped up my third parameterized VIP. This one is a parameterized GPIO VIP, and this is a classic case where using `defines would not have sufficed, since you normally have multiple GPIO interfaces on a chip each requiring different port-width. I had earlier blogged as to why `define will not work in such a scenario.

Continuing with our exposition of the parameterized classes, today we will discuss some details of the vmm_channel and how to use these channels for parameterized transactions.

In an earlier blog entry I had discussed parameterized transactions. Ever since VMM 1.1 release, vmm_channel supports parameterized transactions, though this support is not enabled by default.

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SyntaxHighlighter for SystemVerilog

24Nov09

There seems to be a good number of people who are blogging on SystemVerilog. And a good percentage of these blogs are powered by wordpress.

When I set off blogging, I kind of missed a good syntaxhighlighter for SystemVerilog. Well there are a number of wordpress plugins that do syntax highlighting job for you, but none supports SystemVerilog. Continue reading

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Implementing Parameterized Transaction Descriptors

04Nov09

Parameters (generics in VHDL) have been popular with RTL designers as an aid to make the designs generic. Fortunately, SystemVerilog supports parameterized classes and interfaces.

So how are parameters useful while implementing generic VIPs? Is it not sufficient to pass a configuration object to the VIP and maneuver the VIP configurability with that object? Continue reading

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