Passing the buck to a thread Dec 3 2014

    Hardware is concurrent by nature. And so are testbenches. In context of UVM, the run_phase of each testbench component, executes concurrently with other components. Forking a separate thread for each...

    fork

    Modelling Dynamic Timers in SystemVerilog Dec 2 2014

    When testbenching certain embedded systems, we often come across scenarios where we need to keep a tab on a packet or signal appearing in a periodic fashion. One such scenario is the keepalive ethernet...

    systemverilog

    SystemVerilog Inline Constraint Gotcha Nov 10 2014

    SystemVerilog UVM sequence generates interesting scenerios by randomizing and constraining the data items of the sequence item class. Generally, the constraints are specified in the sequence item class...

    systemverilog

    Variable hiding considered harmful Oct 24 2014

    Welcome to the brand new SystemVerilog blog! DVCon has gone global this year. This September, Bengaluru witnessed the first edition of DVCon India. And last week Accellera concluded the first European...

    systemverilog