SystemVerilog Snippets for VIM users

20Jan10

Just in case you are an Emacs user, you can download and use the equivalent snippets for Emacs from this link. As far as possible, I am using a common codebase for VIM and Emacs SV snippets. So if you use VIM, your snippets would seem much familiar to a colleague at work who loves Emacs.

Just like Emacs, multiple packages are available for VIM that enable use of code snippets within VIM. Of these I used a package named SnipMate for the purpose of exploring VMM snippets in VIM. If you have not used SnipMate before, the following YouTube video provides a wonderful introduction to the package and its use. Continue reading

Filed: OVM, SystemVerilog, Vim, VMM | | 4 Comments

SystemVerilog Snippets for Emacs

17Dec09

SystemVerilog is a huge language and is still growing. To boot we have two separate verification methodologies (VMM and OVM). It is heartening to see some unification effort by Accellera. But I believe VMM and OVM will still be around for at least a couple of years.

To ease up coding effort, VMM provides vmmgen utility (which seems broken in the recently announced 1.2 release). OVM on the other hand has a couple of utilities available in the contrib area of the OVM World.

Being an Emacs addict, I always craved to have these capabilities as part of Emacs. Continue reading

Filed: Emacs, OVM, SystemVerilog, VMM | | 4 Comments

A note on VMM Channel and its Parameterization

27Nov09

I just wrapped up my third parameterized VIP. This one is a parameterized GPIO VIP, and this is a classic case where using `defines would not have sufficed, since you normally have multiple GPIO interfaces on a chip each requiring different port-width. I had earlier blogged as to why `define will not work in such a scenario.

Continuing with our exposition of the parameterized classes, today we will discuss some details of the vmm_channel and how to use these channels for parameterized transactions.

In an earlier blog entry I had discussed parameterized transactions. Ever since VMM 1.1 release, vmm_channel supports parameterized transactions, though this support is not enabled by default.

Filed: SystemVerilog, VMM | | No Comments

SyntaxHighlighter for SystemVerilog

24Nov09

There seems to be a good number of people who are blogging on SystemVerilog. And a good percentage of these blogs are powered by wordpress.

When I set off blogging, I kind of missed a good syntaxhighlighter for SystemVerilog. Well there are a number of wordpress plugins that do syntax highlighting job for you, but none supports SystemVerilog. Continue reading

Filed: Meta, SystemVerilog | | No Comments

Implementing Parameterized Transaction Descriptors

04Nov09

Parameters (generics in VHDL) have been popular with RTL designers as an aid to make the designs generic. Fortunately, SystemVerilog supports parameterized classes and interfaces.

So how are parameters useful while implementing generic VIPs? Is it not sufficient to pass a configuration object to the VIP and maneuver the VIP configurability with that object? Continue reading

Filed: SystemVerilog, VMM | | No Comments

Exploring SystemVerilog Parameterized Classes

27Sep09

Recently Adiel Khan of Synopsys wrote a weblog on the virtues of using parameterized classes for implementing reusable VMM VIP's. It seems support for parameterized classes has matured up quite a bit in the latest release of SV compilers.

In his blog, Adiel concludes that `define macros should be preferred over using parameterized classes. In this blog entry, I will try to focus on some of the virtues of parameterized classes. Continue reading

Filed: SystemVerilog, VMM | | 3 Comments

Packing and Unpacking VMM Transactions

29Jul09

VMM recommends defining byte_pack and byte_unpack methods for each transaction descriptor class. Let us first understand exactly how and why these methods are useful.

The figure below depicts the various abstraction layers in a typical VMM-based verification platform. The concept of a transaction is central to VMM and a transaction transcends through all the different layers. Continue reading

Filed: SystemVerilog, VMM | | No Comments

Copying Arrays and Queues in SystemVerilog

25Jul09

Since the payload in many transactions constitutes of multiple data bytes, it is usually represented by a fixed-size or dynamic array. Often there is a requirement to replicate the array (for example in the VMM mandated copy function).

SystemVerilog provides various ways of achieving this end. Often it is done by copying all the elements .... Continue reading

Filed: SystemVerilog, VMM | | 1 Comment

Use visual-line-mode instead of longlines-mode

23Jul09

longlines-mode has a lot of issues with weblogger. It seems that visual-line-mode is much better. I have been using it for some time now, without any issue.

Here is my new weblogger setup … Continue reading

Filed: Emacs, Meta | | 12 Comments

The VMM way of describing transactions

22Jul09

As one starts building a Verification IP, the first task is to identify the various data transactions that the Design Under Test supports. Some of these transactions would be low-level — quite specific to the pin interfaces of the module. For example if the DUT supports I2C interface, it is imperative for the verification IP to have an I2C transaction descriptor class. In addition, on top of the low-level interfaces, higher abstraction level data transactions would often ride. Continue reading

Filed: SystemVerilog, VMM | | No Comments